GS81332QT19CE-250M Datasheet, PDF (1/30 Pages) GSI Technology – Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+ 1.8

165-Bump CCGA
Military Temp
Preliminary
GS82612QT19/37CE-350M/250M
GS81332QT19/37CE-350M/250M
GS8692QT19/37CE-350M/250M
Rad-Hard SRAM
288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+^TM
350 MHz–250 MHz
1.8 V V_DD
1.8 V and 1.5 V I/O
Features
• Aerospace-Level Product
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump Ceramic Column Grid Array (CCGA) package
Radiation Performance
• Total Ionizing Dose (TID) > 200krads(Si)
• Soft Error Rate (SER) = TBR
• Neutrons = TBR
• Single Event Latchup Immunity > 80 MeV.cm²/mg (100C)
SigmaQuad™ Family Overview
The GS82612QT19/37CE, GS81332QT19/37CE, and
GS8692QT19/37CE are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb),
150,994,944-bit (144Mb), and 75,497,472-bit (72Mb) SRAMs.
These SigmaQuad SRAMs comprise a family of low power,
low voltage HSTL I/O Radiation-Hardened (Rad-Hard)
SRAMs designed to operate in High Radiation environments.
Clocking and Addressing Schemes
The Rad-Hard SigmaQuad-II+ SRAMs are synchronous
devices. They employ two input register clock inputs, K and K.
K and K are independent single-ended clock inputs, not
differential inputs to a single differential clock input buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaQuad-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 8M x 36 has an 4M
addressable index).
tKHKH
tKHQV
Parameter Synopsis
-350M
2.86 ns
0.45 ns
-250M
4.0 ns
0.45 ns
Rev: 1.01 7/2017
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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