GS81280Z36GT-200IV Datasheet, PDF (1/22 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

GS81280Z18/36GT-xxxV
100-Pin TQFP
Commercial Temp
Industrial Temp
144Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz–200 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS81280Z18/36GT-xxxV is a 144Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS81280Z18/36GT-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS81280Z18/36GT-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
-333 -250 -200 Unit
2.5
2.5
3.0
ns
3.0
4.0
5.0
ns
530 430 360 mA
580 460 390 mA
4.5
5.5
6.5
ns
4.5
5.5
6.5
ns
400 360 285 mA
420 380 320 mA
Rev: 1.01 5/2017
1/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology