G2995 Datasheet, PDF (9/12 Pages) Global Mixed-mode Technology Inc – DDR Termination Regulator

Global Mixed-mode Technology Inc.
G2995
Typical Application Circuits
There are several application circuits shown in Figure
2 through 8 to illustrate some of the possible configu-
rations of the G2995. Figure 2~4 are the SSTL-2 ap-
plications. For the majority of applications that imple-
ment the SSTL-2 termination scheme, it is recom-
mended to connect all the input rails to 2.5V rail, as
seen in Figure 2. This provides an optimal trade-off
between power dissipation and component count.
V_DDQ=2.5V
V_DDQ
V_REF
V_DD=2.5V
C_IN ⁺
AV_IN
V_SENSE
PV_IN
V_TT
GND
+
V_REF=1.25V
C_REF
V_TT=1.25V
+
C_OUT
Figure 2. Recommended SSTL-2 Implementation
In Figure 3, the power rails are split. The power rail of
the output stage (PVIN) can be as low as 1.8V, the
power rail of the analog circuit (AVIN) is operated
above 2V. The lower output stage power rail can lower
the internal power dissipation when sourcing from the
device and improve the efficiency, but the disadvan-
tage is the maximum continuous current sourcing from
V_TT is reduced. This configuration is applied when the
power dissipation and efficiency are concerned.
V_DDQ=2.5V
V_DDQ
V_REF
AV_IN=1.8V or 5.5V
PV_IN=1.8V
C_IN ⁺
AV_IN
V_SENSE
PV_IN
V_TT
GND
+
V_REF=1.25V
C_REF
V_TT=1.25V
+
C_OUT
Figure 3. Lower Power Dissipation SSTL-2 Implementation
In Figure 4, the power rail of the output stage (PVIN) is
connected to 3.3V to increase the maximum continu-
ous current sourcing from V_TT. AVIN should be always
equal to or larger than PVIN. This configuration can
increase the source capability of this device, but the
power dissipation increases at the same time. It
should be more careful to prevent the junction tem-
perature from exceeding the maximum rating. Be-
cause of this risk, it is not recommended to supply the
output stage power rail (PVIN) with a voltage higher
than a nominal 3.3V rail.
V_DDQ=2.5V
V_DDQ
V_REF
AV_IN=3.3V or 5V
PV_IN=3.3V
C_IN ⁺
AV_IN
V_SENSE
PV_IN
V_TT
GND
+
V_REF=1.25V
C_REF
V_TT=1.25V
+
C_OUT
Figure 4. SSTL-2 Implementation with higher voltage rails
Ver: 1.7
May 10, 2005
TEL: [phone]
http://www.gmt.com.tw
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