G1420 Datasheet, PDF (19/20 Pages) Global Mixed-mode Technology Inc – 2W Stereo Audio Amplifier

Global Mixed-mode Technology Inc.
G1420
MUTE and SHUTDOWN Mode Operations
G1420 implements the mute and shutdown mode
operations to reduce supply current, I_DD, to the ab-
solute minimum level during nonuse periods for
battery-power conservation. When the shutdown
pin (pin 8) is pulled high, all linear amplifiers will be
deactivated to mute the amplifier outputs. And
G1420 enters an extra low current consumption
state, I_DD is smaller than 5µA. If pulling mute-in pin
(pin 11) high, it will force the activated linear ampli-
fier to supply the VDD/2 dc voltage on the output to
mute the AC performance. In mute mode operation,
the current consumption will be a little different be-
tween BTL, SE. (SE < BTL) Typically, the supply
current is about 2.5mA in BTL mute operation.
Shutdown and Mute-In pins should never be left
unconnected, this floating condition will cause the
amplifier operations unpredictable.
Optimizing DEPOP Operation
Circuitry has been implemented in G1420 to mini-
mize the amount of popping heard at power-up and
when coming out of shutdown mode. Popping oc-
curs whenever a voltage step is applied to the
speaker and making the differential voltage gener-
ated at the two ends of the speaker. To avoid the
popping heard, the bypass capacitor should be
chosen promptly, 1/(C_Bx100kΩ) ≦ 1/(C_I*(R_I+R_F)).
Where 100kΩ is the output impedance of the
mid-rail generator, C_B is the mid-rail bypass ca-
pacitor, C_I is the input coupling capacitor, R_I is the
input impedance, R_F is the gain setting impedance
which is on the feedback path. C_B is the most im-
portant capacitor. Besides it is used to reduce the
popping, C_B can also determine the rate at which
the amplifier starts up during startup or recovery
from shutdown mode.
De-popping circuitry of G1420 is shown on Figure D.
The PNP transistor limits the voltage drop across
the 50kΩ by slewing the internal node slowly when
power is applied. At start-up, the voltage at
BYPASS capacitor is 0. The PNP is ON to pull the
mid-point of the bias circuit down. So the capacitor
sees a lower effective voltage, and thus the charg-
ing is slower. This appears as a linear ramp (while
the PNP transistor is conducting), followed by the
expected exponential ramp of an R-C circuit.
Bypass
50 kΩ
VDD
100 kΩ
100 kΩ
Figure D
Junction Temperature Measurement
Characterizing a PCB layout with respect to thermal
impedance is very difficult, as it is usually impossi-
ble to know the junction temperature of the IC.
G1420 TJ (pin 2) sources a current inversely pro-
portional to the junction temperature. Typically TJ
sources–120µA for a 5V supply at 25°C. And the
slope is approximately 0.22µA/°C. As the resistors
have a tolerance of ±20%, these values should be
calibrated on each device. When the temperature
sensing function is not used, TJ pin can be left
floating or tied to VDD to reduce the current con-
sumption.
Temperature sensing circuit is shown on Figure E.
VDD
R
R
5R
TJ
Figure E
Ver: 1.5
Aug 04, 2005
TEL: [phone]
http://www.gmt.com.tw
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