GS2961A Datasheet, PDF (95/104 Pages) Gennum Corporation – Ancillary data extraction

Table 4-19: ANC Extraction FIFO Access Registers
Address
Register Name
Bit
800h -
BFFh
ANC_PACKET_BANK
15-0
Description
Extracted Ancillary Data 91024 words.
Bit 15-8: Most Significant Word (MSW).
Bit 7-0: Least Significant Word (LSW).
See Section 4.18.8.
Legend:
R = Read only
ROCW = Read Only, Clear on Write
R/W = Read or Write
W = Write only
4.21 JTAG Test Operation
When the JTAG/HOST pin of the GS2961A is set HIGH and the SMPTE_BYPASS pin is
LOW, the host interface port is configured for JTAG test operation. In this mode, pins E7,
F8, F7, and E8 become TDO, TCK, TMS, and TDI. In addition, the RESET_TRST pin
operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly.
2. Under control of a host processor for applications such as system power on self
tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with the JTAG/HOST input
signal. This is shown in Figure 4-42.
Application HOST
GS2961A
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
Figure 4-42:In-Circuit JTAG
In-circuit ATE probe
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
R/W
R
Default
0
95 of 104