GS7005 Datasheet, PDF (9/12 Pages) Gennum Corporation – Complete Serial Digital Video Receiver

DETAILED DESCRIPTION
The main functional blocks of the GS7005 are:
1. PECL input buffer
2. Fixed Gain Equalizer
3. Slicer
4. NRZI Decoder & SMPTE Descrambler
5. TRS Detector
6. Signal Lock Detect
7. Serial to Parallel Convertor
Refer to the Functional Block Diagram on the front page of
this data sheet.
1. PECL INPUT BUFFER
This differential input buffer features a built-in load
termination for the incoming SDI signal. The load is
characterized as 75Ω over a wide frequency range and is
made up of an internal fixed resistor and current source.
2. FIXED GAIN EQUALIZER
The Fixed Gain Equalizer stage is used to compensate the
frequency dependent loss of the SDI signal through co-axial
cable. The SDI signal is connected to the input pins (SDI/
SDI) either differentially or single ended. The input signal
passes through a fixed gain equalizing stage whose
frequency response closely matches the inverse cable loss
characteristic. The equalizer typically provides 100m of
coaxial cable equalization. The frequency response is
optimized for maximum cable length. For short cable
lengths (<10m), bypass the equalizing stage by setting the
EQ control pin to a logic HIGH level. If an external equalizer
is used, bypass the internal equalizer of the GS7005 to
avoid over-equalization (see Figure 12).
3. POST EQUALIZATION SLICER
The Post Equalization Slicer stage slices the equalized
signal, thereby eliminating any DC offset due to the AC
coupling requirement of the SDI signal. Using a differential
comparator, the received signal voltage is compared to a
midway voltage, known as the baseline or the slicing level.
The sliced signal is then applied to the NRZI/SMPTE
Decoder/Descrambler and the PLL MUX.
4. NRZI DECODER & SMPTE DESCRAMBLER
To comply with the the ANSI/SMPTE 259M standard, use a
scrambled, polarity free NRZI code. The polynomial
generator for the scrambler is G1(X) = X⁹+X⁴+1. The NRZI
code is produced by a second polynomial, G2(X) = X+1.
The NRZI Decoder and SMPTE Descrambler blocks within
the GS7005 regenerate the original NRZ unscrambled
signal by applying the same algorithm to the received
signal. For data structures that do not require de-
scrambling and NRZI-NRZ conversion, bypass this block
by setting the SMPTE pin to logic HIGH.
5. PLL, MUX and f/10
The PLL clock recovery circuitry provides an internal,
synchronous 270MHz clock. The 27MHz parallel data clock
is derived from the serial clock through a resettable
frequency divider. To synchronize the parallel clock signal,
set the frequency divider to the initial state at the same time
the state machine has detected the Timing Reference
Signal (TRS).
The PLL self-centres the VCO to approximately 29MHz
when there are no input data transitions. This allows the PLL
to lock when a valid signal within the lock range is applied.
However, if the GS7005 detects a spurious input with
random data transitions, the centering function of the VCO
is inhibited. This causes the VCO control voltage to drift to a
low clamp level resulting in a VCO frequency of 22MHz. To
prevent this “latch-up” condition implementation of a high
impedance (1MΩ) bleed resistor across the C1 and C2
(loop filter, pins 16 and 17) is recommended. Due to the
large resistance value, the effect on IJT is negligible (see
Figure 11).
6. TRS DETECTOR
The TRS Detector detects the TRS headers (EAV and SAV).
It consists of a word-counter, bit-counter and control state-
machine. The bit-counter is reset by either the decoded
data or the output of the state-machine. In a normal case,
the state-machine output is LOW. The reset of the bit
counter is active LOW so that the bit-counter will be started
when the data is HIGH. The detection of a valid TRS header
is indicated by a level change of the H-signal pin.
7. SIGNAL LOCK DETECT
When there are no input data transitions, the CD pin goes to
a HIGH logic level and forces the VCO to the centre
frequency as described in section 5, PLL, MUX, and f/10.
This output can be used to control an external transistor
and LED. When there are input data transitions (valid or
invalid), the CD pins goes to a LOW logic state.
The locking state of the PLL is indicated by the output
LOCK signal being set to a logical HIGH level. This pin
however, may have periodic transitions to a LOW logic state
of 64µs maximum duration even though the device is
properly locked. The parallel data signal integrity is not
affected under these conditions. Therefore, the LOCK pin
should not be used as a logic control signal if a steady level
is required. The output voltage remains in a logic HIGH
state for a sufficient period and can be used to drive visual
indicators such as LEDs.
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