GS1582_09 Datasheet, PDF (75/115 Pages) Gennum Corporation – Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner

Table 4-39: Serial Digital Output Rates
Supplied PCLK Rate
Serial Digital
Output Rate
74.25 or
74.25/1.001 MHz
148.5 or
148.5/1.001MHz
13.5MHz
27MHz
1.485 or
1.485/1.001Gb/s
1.485 or
1.485/1.001Gb/s
270Mb/s
270Mb/s
Pin Settings
SD/HD
LOW
20bit/10bit
HIGH
LOW
LOW
HIGH
HIGH
HIGH
LOW
4.11 Internal ClockCleaner^TM PLL
To obtain a clean clock signal for serialization and transmission, an external VCO signal
is locked to the input PCLK via the GS1582's integrated phase-locked loop. This high
quality analog PLL has a bang-bang implementation, which automatically narrows the
loop bandwidth in the presence of jitter, allowing the GS1582 to significantly attenuate
jitter on the incoming PCLK.
4.11.1 External VCO
The GS1582 requires the GO1555 external voltage controlled oscillator as part of its
internal PLL.
Power for the external VCO is generated by the GS1582 from an integrated voltage
regulator. The internal regulator uses +3.3V supplied on the CP_VDD / CP_GND pins to
provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz signal for the PLL, input on the VCO pin of the
device. See Typical Application Circuit (Part A) on page 109.
NOTE: The VCO_VCC output voltage is guaranteed to be 2.5V only when supplying
power to the GO1555. The VCO_VCC pin should not be shorted to GND under any
circumstances.
4.11.2 Loop Filter
The GS1582 PLL loop filter is an external first order filter formed by a series RC
connection as shown in the Typical Application Circuit (Part A) on page 109. The loop
filter resistor value sets the bandwidth of the PLL and the capacitor value controls its
stability and lock time. A loop filter resistor value between 1Ω to 20Ω and a loop filter
capacitor value between 1μF to 33μF are recommended.
The GS1582 uses a non-linear, bang-bang, PLL, therefore its bandwidth scales with the
input jitter amplitude - greater input jitter results in a smaller loop bandwidth causing
more of the input jitter to be rejected. For a given input jitter amplitude, a smaller loop
filter resistor produces a narrower loop bandwidth. With an input jitter amplitude of
300ps, for example, the PLL bandwidth can be adjusted from 2KHz to 40KHz by varying
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner^TM
Data Sheet
40117 - 3
March 2009
75 of 115