GS9092A_10 Datasheet, PDF (7/63 Pages) Gennum Corporation – GenLINX III 270Mb/s Serializer for SDI and DVB-ASI

Table 1-1: Pin Descriptions (Continued)
Pin Number Name
12
IOPROC_EN
13
JTAG/HOST
14
RESET
15, 45
CORE_VDD
Timing
Type
Non
Input
Synchronous
Non
Input
Synchronous
Non
Input
Synchronous
Non
Input
Synchronous Power
Description
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device
are enabled:
• SMPTE 352M Payload Identifier Packet Generation and
Insertion
• Illegal Code Remapping
• EDH Generation and Insertion
• Ancillary Data Checksum Insertion
• TRS Generation and Insertion
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE
register accessible via the host interface.
When this pin is set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for video mode or
ancillary data insertion mode, the IOPROC_EN pin must be set
HIGH.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured as GSPI pins for normal host interface operation.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting or
to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all functional blocks will be set to default
conditions ,SDO and SDO are muted, and all input signals become
high impedance with the exception of the STAT pins which will be
driven LOW.
When set HIGH, normal operation of the device resumes 10usec
after the LOW-to-HIGH transition of the RESET signal.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all functional blocks will be set to default and
the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
NOTE: For power on reset requirements please see Device Power Up
on page 58.
Power supply for digital logic blocks. Connect to +1.8V DC.
NOTE: For power sequencing requirements please see Device Power
Up on page 58.
GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Data Sheet
34715 - 4
May 2010
7 of 63