GS9005A Datasheet, PDF (4/12 Pages) Gennum Corporation – Serial Digital Receiver

SERIAL
DATA OUT
(SD0)
SERIAL
CLOCK OUT
(SCK)
tD
tD
50%
50%
Fig.1 Waveforms
AGC
V_CC1 V_EE1 CAP A/D SSI V_EE2 V_CC4
DDI
DDI
V_CC2
SDI
SDI
43
5
6
7
8
9
2
28 27 26
25
24
23
GS9005A
TOP VIEW
22
21
ƒ/2 EN
10
20
V_EE3
11
12 13
19
14 15 16 17 18
SD0
SD0
SC0
SC0
SS1
SS0
CD
LOOP R_VCO0 R_VCO1 R_VCO2 OEM R_VCO3 V_CC3
FILT
Fig. 2 GS9005A Pin Connections
GS9005 & GS9005A PIN DESCRIPTIONS
PIN NO. SYMBOL TYPE
DESCRIPTION
1
A/D
Input
Analog/Digital Select. TTL compatible input used to select the input signal source. A logic HIGH routes the
Equalizer inputs (pins 8 and 9) to the PLL and a logic LOW routes the Direct Digital inputs (pins 5 and 6)
to the PLL.
2
AGC CAP Input
3
V_EE1
4
V_CC1
5,6 DDI/DDI Input
7
V_CC2
8,9 SDI/SDI Input
AGC Capacitor. Connection for the AGC capacitor.
Power Supply. Most negative power supply connection. (Equalizer)
Power Supply. Most positive power supply connection. (Equalizer)
Direct Data Inputs (true and inverse). Pseudo-ECL, differential serial data inputs. These are selected
when the A/D input (pin 1) is at logic LOW and are self biased to 1.2 volts below V_CC. They may be
directly driven from true ECL drivers when V_EE = -5V and V_CC= 0 V.
Power Supply. Most positive power supply connection. ( Phase detector, A/D select, carrier detect).
Serial Data Inputs (true and inverse). Differential analog serial data inputs. Inputs must be AC
coupled and may be driven single ended. These inputs are selected when the A/D input (pin 1) is
logic HIGH.
10 ƒ/2 EN
11
V_EE3
Input
12
LOOP FILT
ƒ/2 Enable-TTL compatible input used to enable the divide by 2 function.
Power Supply. Most negative power supply connection. (VCO, Mux, Standard Select)
Loop Filter. Node for connecting the loop filter components.
13
R_VCO0
14
R_VCO1
15
R_VCO2
16 OEM
Input
Input
Input
Output
VCO Resistor 0. Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set to logic 0,0. A resistor is connected from this pin to V_EE.
VCO Resistor 1. Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to V_EE.
VCO Resistor 2. Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to V_EE.
Output Eye Monitor Analog voltage representing the serial bit stream after equalization but before reslicing.
17
R_VCO3
Input
VCO Resistor 3. Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to V_EE.
520 - 28 - 11
4