GS9023B Datasheet, PDF (35/56 Pages) Gennum Corporation – Embedded Audio CODEC

When the ANCI pin or “ADEL” bit is LOW, all ancillary data packets remain in the video
signal. See Figure 3-13.
TRS can also be removed from a 525/625 D2 video signal when the TRS pin is set HIGH
or the “VSEL” and “D2_TRS” bits of Host Interface Register #0h are set HIGH.
Video signal before GS9023B
Empty
Empty
Empty
Video signal after GS9023B Removal of Audio Group 1 & Extended
Audio Group 1 (ANCI = HIGH or "VSEL" and "ADEL" = HIGH)
Figure 3-12: Removal of Audio Group 1 with Extended Audio, ADEL=HIGH
Video signal before GS9023B
Empty
Empty
Video signal after GS9023B Removal of Audio Group 1 & Extended Audio Group 1
(ANCI = LOW or "VSEL" = HIGH and "ADEL" = LOW)
Figure 3-13: Removal of Audio Group 1 with Extended Audio, ADEL=LOW
3.2.4 Audio Clock Input
The user must input a master audio clock (128 fs: 6.144MHz) at the ACLK clock terminal.
This clock must be synchronized with the video signal input to the GS9023B. The audio
word clock inputs WC_INA and WC_INB must be grounded.
NOTE: The long term jitter present on the ACLK must be less than half the audio clock
period.
GS9023B GENLINX® II GS9023B Embedded Audio
CODEC
Data Sheet
37954 - 2
December 2009
35 of 56
Proprietary & Confidential