GS9060 Datasheet, PDF (31/61 Pages) Gennum Corporation – HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver

GS9060 Data Sheet
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing information to maintain synchronization.
The FW_EN/DIS input pin controls the synchronization mechanism of the flywheel.
When this input signal is LOW, the flywheel will re-synchronize all pixel and line
based counters on every received TRS ID word.
When FW_EN/DIS is held HIGH, re-synchronization of the pixel and line based
counters will only take place when a consistent synchronization error has been
detected. Two consecutive video lines with identical TRS timing different to the
current flywheel timing must occur to initiate re-synchronization of the counters.
This provides a measure of noise immunity to internal and external timing signal
generation.
The flywheel will be disabled should the LOCKED signal or the RESET_TRST
signal be LOW. A LOW to HIGH transition on either signal will cause the flywheel
to re-acquire synchronization on the next received TRS word, regardless of the
setting of the FW_EN/DIS pin.
3.7.3 Switch Line Lock Handling
The principal of switch line lock handling is that the switching of synchronous video
sources will only disturb the horizontal timing and alignment of the stream, whereas
the vertical timing remains in synchronization.
To account for the horizontal disturbance caused by a synchronous switch, it is
necessary to re-synchronize the flywheel immediately after the switch has taken
place. Rapid re-synchronization of the GS9060 to the new video standard can be
achieved by controlling the flywheel using the FW_EN/DIS pin.
At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW
to HIGH transition at this pin is detected anywhere within the active line, the
flywheel will re-synchronize immediately to the next TRS word. This is shown in
Figure 3-2.
To ensure switch line lock handling, the FW_EN/DIS signal should be LOW for a
minimum of one PCLK cycle (maximum one video line) anywhere within the active
portion of the line on which the switch has taken place.
22208 - 8 January 2007
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