GS1582 Datasheet, PDF (29/114 Pages) Gennum Corporation – Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

GS1582 Data Sheet
PCLK
LUMA DATA OUT
CHROMA DATA OUT
H
V
F
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
3FF
000
000
XYZ
(sav)
H_Blanking: V_Blanking: F_Digital TIMING - HD 20-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
H
V
F
3FF
3FF
000
000
000
000
XYZ
(eav)
XYZ
(eav)
H_Blanking: V_Blanking: F_Digital TIMING AT EAV - HD 10-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
H
V
F
3FF
3FF
000
000
000
000
XYZ
(sav)
XYZ
(sav)
H_Blanking: V_Blanking: F_Digital TIMING AT SAV - HD 10-BIT INPUT MODE
PCLK
CHROMA DATA OUT
LUMA DATA OUT
H
H SIGNAL TIMING:
V
H_CONFIG = LOW
F
H_CONFIG = HIGH
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(SAV)
H_Blanking: V_Blanking: F_Digital TIMING - SD 20-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
H
V
F
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H_Blanking: V_Blanking: F_Digital TIMING - SD 10-BIT INPUT MODE
Figure 4-2: H_Blanking, V_Blanking, F_Digital Timing
4.3.2 CEA 861 Timing
The GS1582 extracts timing information from externally provided HSYNC, VSYNC,
and DE signals when CEA 861 timing mode is selected by setting DETECT_TRS
= LOW and the TIM_861 = HIGH.
40117 - 1 November 2007
29 of 114