GS1535A_06 Datasheet, PDF (22/27 Pages) Gennum Corporation – Multi-Rate SDI Automatic Reclocker

GS1535A / GS9065A Data Sheet
4.9 DVB-ASI Operation
The GS1535A/9065A will also re-clock DVB-ASI at 270 Mb/s. When reclocking
DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If
ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present
in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note
that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device
is in Auto mode, consequently the GS1535A/9065A will not lock to that data rate.
4.10 Lock Indicator
The LOCK DETECT signal, LD, is an active high output which indicates when the
PLL is locked.
The internal lock logic of the GS1535A/9065A includes a system which monitors
the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a
monitor to detect harmonic lock.
4.11 Output Drivers
The device’s serial digital data outputs (DDO/DDO) have a nominal voltage of
800mv single ended or 1600mV differential when terminated into a 50Ω load.
4.12 Output Mute
The DDO_MUTE pin is provided to allow muting of the re-timed output.
When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW
will force the serial digital outputs DDO/DDO to mute. However, if the
GS1535A/9065A is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS =
HIGH), DDO_MUTE will have no effect on the output.
31497 - 4 June 2006
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