GS2985 Datasheet, PDF (20/45 Pages) Gennum Corporation – Uses standard 27MHz crystal

Table 4-1: Input Trace Equalization Operation
EQn_EN Setting
LOW
HIGH
Trace Equalization Range
Low
Medium
The default peak-gain setting upon power-up is optimized for compensating the
high-frequency losses associated with approximately 10 inches of 5-mil stripline in FR4
material.
The EQn_EN pins are multiplexed with the serial host interface pins. The EQn_EN functionality
is enabled when pin HIF is tied HIGH, as shown in Table 4-2:
Table 4-2: EQn_EN Pins Multiplexed
Pin
Function
SDI/EQ0_EN
SDO/EQ1_EN
SCK/EQ2_EN
CS/EQ3_EN
Active-high logic input to enable trace-equalization for high-speed input channel 0.
Active-high logic input to enable trace-equalization for high-speed input channel 1.
Active-high logic input to enable trace-equalization for high-speed input channel 2.
Active-high logic input to enable trace-equalization for high-speed input channel 3.
4.4 4:1 Input Mux
The GS2985 incorporates a 4:1 input mux, which allows the connection of four independent
streams of video/data. There are four differential inputs (DDI[3:0] / DDI[3:0]). The active channel
can be selected via the DDI_SEL[1:0] pins as shown in Table 4-3.
Table 4-3: Input Selection Table
DDI_SEL[1:0]
00
01
10
11
Selected Input
DDI0
DDI1
DDI2
DDI3
The DDI_SEL pins include internal pull-downs, which pull the input voltage LOW if either pin
is unconnected. Active circuitry associated with the input buffers and trace EQ can only be
turned on for the selected input. Inputs which are not selected have their input buffers and trace
EQs turned OFF to save power. Unused inputs can be either left floating, or tied to VCC.
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 5
July 2012
20 of 45
Proprietary & Confidential