GS4915_09 Datasheet, PDF (18/27 Pages) Gennum Corporation – ClockCleaner

When LOCK is HIGH, the output clock will be low-jitter and locked to the selected input
clock. But when LOCK is LOW in Forced Output mode, the output clock should not be
used.
3.5 Output Clock Frequency and Jitter
The frequency and jitter of the output clock are determined by:
• the frequency of the input clock,
• the differential or single-ended input and output clocks,
• the selected frequency mode,
• the selected bypass mode, and
• the setting of the DOUBLE pin.
When the DOUBLE pin is set HIGH, the output clock frequency will be double the input
only when the selected input clock frequency is determined to be 74.25MHz ± 0.4%.
Otherwise, the setting of the DOUBLE pin will have no effect on the frequency of the
output clock.
The output clock will be low jitter when the LOCK pin is HIGH. The only exception to this
is if operating in Manual Bypass mode, see Section 3.4.2.Table 3-4, Table 3-5, and
Table 3-6 summarize the output frequency and LOCK behaviour of the device given the
frequency of the input clock, the selected frequency mode, and the setting of the
DOUBLE pin for Autobypass, Manual Bypass, and Forced Output modes, respectively.
In each table, 'X' indicates a "don't care" condition.
Table 3-4: Output Behaviour in Autobypass Mode
FCTRL[1:0]
Auto [00]
Fixed – 27MHz
[01]
Input
27MHz
74.25MHz
148.5MHz
Other
27MHz
74.25MHz
148.5MHz
Other
DOUBLE
X
0
1
X
X
X
X
X
X
LOCK
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
Output
27MHz
74.25MHz
148.5MHz
148.5MHz
Input
27MHz
74.25MHz
148.5MHz
Input
GS4915 ClockCleaner™
Data Sheet
39145 - 5
June 2009
18 of 27