GS2975A Datasheet, PDF (18/27 Pages) Gennum Corporation – HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs

4.4 Frequency Acquisition Loop — The Phase-Frequency Detector
An external crystal of 14.140MHz is used as a reference to keep the VCO centered at the
last known data rate. This allows the device to achieve a fast synchronous lock,
especially in cases where a known data rate is interrupted. The crystal reference is also
used to clock internal timers and counters. To keep the optimal performance of the
reclocker over all operating conditions, the crystal frequency must be 14.140MHz,
+/-50ppm. The GO1535 meets this specification and is available from Gennum.
The GO1535 requires an external resistor to be placed in series with the crystal. The
optimal value of this resistor can range from 100 to 150 ohms, and this value will depend
upon the design. For systems which expect to see a higher noise floor, the higher resistor
value is recommended. The higher resistor value will work to decrease the loop gain of
the oscillator, as well as attenuate noise.
The VCO is divided by a selected ratio which is dependant on the input data rate. The
resultant is then compared to the crystal frequency. If the divided VCO frequency and
the crystal frequency are within 1% of each other, the PLL is considered to be locked to
the input data rate.
4.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the input
data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and
a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the
input data transition is aligned to the falling edge of I-clk and the output data is re-timed
on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will
sample a different value than I-clk. In this condition, two extra phase correction signals
will be generated which instructs the charge pump to create larger frequency
corrections for the VCO.
i-PHASE ALIGNMENT
EDGE
I-clk
DATA RE-TIMING
EDGE
q-clk
q-PHASE ALIGNMENT
EDGE
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
0.25UI
0.8UI
Figure 4-2: Phase Detector Characteristics
When the PA loop is active, the crystal frequency and the incoming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the
system jumps to the FA loop.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4
April 2009
18 of 27