GS1671A Datasheet, PDF (123/136 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address
280h
Register Name Bit Name
ACSR_BYTE_0
RSVD
ACSR0
281h
ACSR_BYTE_1
RSVD
ACSR1
282h
ACSR_BYTE_2
RSVD
ACSR2
283h
ACSR_BYTE_3
RSVD
ACSR3
284h
ACSR_BYTE_4
RSVD
ACSR4
285h
ACSR_BYTE_5
RSVD
ACSR5
286h
ACSR_BYTE_6
RSVD
ACSR6
Bit
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
Description
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
R/W
R/W
W
Default
0
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
123 of 136