GX9533 Datasheet, PDF (1/8 Pages) Gennum Corporation – Serial Digital 8x9 Crosspoint

GENLINX ^™II GX9533
Serial Digital 8x9 Crosspoint
FEATURES
• operation beyond 622Mb/s
• accepts SMPTE and PECL input levels
• fully differential signal path
• on-chip PECL current loads eliminate need for
external pull-down resistors
• capable of driving 100Ω differential loads
• very low 500mW power consumption
• additional expansion port input for construction of
larger matrices
• auxiliary monitoring output
• easy to configure
• double latched address inputs with separate load and
configure
• TTL/CMOS compatible control logic inputs
• single 5V power supply
APPLICATIONS
Serial digital video switching; datacom or telecom
switching.
DESCRIPTION
DATA SHEET
The GX9533 is a high speed 8x9 serial digital crosspoint.
An expansion input port eases the design of larger
switching matrices by reducing PCB layers and eliminating
the need for cascaded secondary switching. Decode logic
and double level latching to configure the matrix are
included on chip. Separate LOAD and CONFIGURE inputs
allow for asynchronous configuration and synchronous
switching. These latches can also be made transparent for
asynchronous switching by pulling the LOAD and
CONFIGURE pins high.
In the power saving (PS) mode, the GX9533 has a very low
power consumption of 500mW. This is accomplished by
driving a 400mV output swing into the on-chip 200Ω
differential load termination in the expansion port of the next
GX9533. This architecture provides a significant power
savings and the elimination of external load resistors or
impedance matching resistors. In applications where
standard PECL levels are necessary, the GX9533 can be
configured in "PECL Mode", to drive 800mV p-p into a 100Ω
differential load. The power consumption in this mode
increases to 860mW.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GX9533-CQY
100 pin MQFP Tray
GX9533-CTY
100 pin MQFP Tape
TEMPERATURE
0°C to 70°C
0°C to 70°C
2
AUX IN
16
EXP0..7
16
IN0 .. 7
INPUT
BUFFER
SWITCHING
MATRIX
2
16
OUTPUT
BUFFER
STD/PECL2
STD/PECL1
V_CCO
OUT 0..7
16
AUX
2
CONFIG
CONFIG
LATCH
LOAD
LOAD A
OA0..2
IA0..3
LOAD
LATCH
3
DECODE
4
LOGIC
V_EE
V_CC
Revision Date: August 1999
BLOCK DIAGRAM
Document No. 521 - 41 - 03
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