GS9002 Datasheet, PDF (1/11 Pages) Gennum Corporation – GENLINXTM GS9002 Serial Digital Encoder

GENLINX^™ GS9002
Serial Digital Encoder
DATA SHEET
FEATURES
DEVICE DESCRIPTION
• fully compatible with SMPTE-259M serial digital
standard
The GS9002 is a monolithic bipolar integrated circuit designed
to serialize SMPTE 125M and SMPTE 244M bit parallel digital
• supports up to four serial bit rates to 400 Mb/s
• accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs
signals as well as other 8 or 10 bit parallel formats. This device
performs the functions of sync detection, parallel to serial
conversion, data scrambling (using the X⁹ + X⁴ +1 algorithm),
10x parallel clock multiplication and conversion of NRZ to
• X⁹ + X⁴ + 1 scrambler, NRZI converter and sync
detector may be disabled for transparent data
transmission
D _{• pseudo-ECL serial data and clock outputs}
E • single +5 or -5 volt supply
• 713 mW typical power dissipation (including ECL
D _{pull-down loads).}
N ^{S • 44 pin PLCC packaging}
E ^{N APPLICATIONS}
• 4ƒ_SC, 4:2:2 and 360 Mb/s serial digital interfaces for
M _{IG Video cameras, VTRs, Signal generators}
M S ORDERING INFORMATION
O ^{E Part Number}
Package Type
C ^{D GS9002 - CPM}
44 Pin PLCC
Temperature Range
0° to 70°C
NRZI serial data. It supports any of four selectable serial data
rates from 100 Mb/s to over 360 Mb/s. The data rates are set
by resistors and are selected by an on-board 2:4 decoder
having two TTL level input address lines.
Other features such as a sync detector output, a sync detector
disable input, and a lock detect output are also provided. The
X⁹ + X⁴ + 1 scrambler and NRZ to NRZI converter may be
bypassed to allow the output of the parallel to serial converter
to be directly routed to the output drivers.
The GS9002 provides pseudo-ECL outputs for the serial data
and serial clock as well as a single-ended pseudo-ECL output
of the regenerated parallel clock.
The GS9002 directly interfaces with cable drivers GS9007,
GS9008 and GS9009. The device requires a single +5 volt or
-5 volt supply and typically consumes 713 mW of power while
driving 100 Ω loads. The 44 pin PLCC packaging assures a
small footprint for the complete encoder function.
E _SCRAMBLER/
R ^{W SERIALIZER 26}
SELECT
SYNC DETECT
6
E ^DISABLE
PARALLEL DATA 7-16
OT ^{N IN (10 BITS)}
INPUT
LATCH
SYNC
DETECT
P/S
CONVERTER
SCRAMBLER
NRZ
NRZI
N _FORPLD
SCLK
2:1 MUX
LOCK
3
SYNC DETECT
38
SERIAL DATA
39
SERIAL DATA
42
SERIAL CLOCK
43
SERIAL CLOCK
20
LOCK DETECT
DETECT
PCLK IN ¹⁷
PHASE
FREQUENCY
DETECT
CHARGE
PUMP
VCO
29
REGULATOR CAP
LOOP FILTER ²²
19
PCLK OUT
GS9002
DIV BY 10
GENERATOR
DATA RATE
SWITCH
36 _DRS0
35
DRS1
34 _RVC00
33 _RVC01
32 _RVC02
31
RVC03
Patent No.5,357,220
Revision Date: March 2001
FUNCTIONAL BLOCK DIAGRAM
Document No. 520 - 27 - 08
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. [phone] fax: [phone]
Gennum Japan Corporation C-101 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan tel. [phone] fax [phone]