GL9714 Datasheet, PDF (39/46 Pages) GENESYS LOGIC – PCI ExpressTM PIPE x4 PHY

GL9714 PCI Express^TM PIPE x4 PHY
7.5 Differential Transmitter and Receiver Serial Output
Transmitter Serial Output
Table 7.6 – Transmitter Serial Output
Symbol
Parameter
Min Typ Max Unit
UI
Unit interval
399.88 400 400.12 ps
V_TX-DIFFp-p
V_TX-DE-RATIO
Differential peak to peak output voltage 0.8
De-emphasized
voltage (Ratio)
differential
output _-3.0
T_TX-EYE
Minimum TX eye width
Maximum time between the jitter
T_{TX-EYE-MEDIAN-to-MAX-JITTER} median and maximum deviation from
the median
T_TX-RISE,
T_TX-FALL
V_TX-CM-ACp
D+/D- TX output rise/fall time
RMS AC peak common mode output
voltage
V_{TX-CM-DC-ACTIVE-IDLE-DELTA}
Absolute delta of DC common mode
voltage during L0 and electrical idle
V_{TX-CM-DC-LINE-DELTA}
Absolute delta of DC common mode
voltage between D+ and D-
V_{TX-IDLE-DIFFp}
Electrical idle differential peak output
voltage
V_{TX-RCV-DETECT}
The amount of voltage change allowed
during receiver detection
0.7
-
0.125
-
0
0
0
-
V_TX-DC-CM
The TX DC common mode voltage
0
I_TX-SHORT
TX short circuit current limit
-
T_TX-IDLE-MIN
T_{TX-IDLE-SET-TO-IDLE}
T_{TX-IDLE-TO-DIFF-DATA}
Minimum time spent in electrical idle
50
Maximum time to transition to a valid
electrical idle after sending an electrical -
idle ordered set
Maximum time to transition to valid TX
specifications after leaving an electrical -
idle condition
RL_TX-DIFF
Differential return loss
12
RL_TX-CM
Common mode return loss
6
Z_TX-DIFF-DC
DC differential TX impedance
80
L_TX-SKEW
Lane-to-lane output skew
-
C_TX
AC coupling capacitor
75
Tcrosslink
Crosslink random timeout
0
-
1.2
V
-3.5 -4.0
dB
-
-
UI
-
0.15
UI
-
-
UI
-
20
mV
-
100
mV
-
25
mV
-
20
mV
-
600
mV
-
3.6
V
-
90
mA
-
-
UI
-
20
UI
-
20
UI
-
-
dB
-
-
dB
100 120
Ω
- 500 + 2UI ps
-
200
nF
-
1
ms
©2004-2007 Genesys Logic Inc. - All rights reserved.
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