GL811E Datasheet, PDF (14/33 Pages) List of Unclassifed Manufacturers – USB 2.0 to ATA / ATAPI Bridge Controller

GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 5 FUNCTION DESCRIPTION
1. USB 2.0 TXCVR
The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling.
2. UTMI (USB 2.0 Transceiver Macrocell Interface) Logic
The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB
protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding,
Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion.
3. SIE (Serial Interface Engine)
The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine
logic to handle USB packets and transactions.
4. PLL
10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS
data processing. 40XPLL block will provide 480MHz for USB HS data transmission.
5. CLKGEN
CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller,
48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO.
6. CPU
The CPU is the control center of GL811E. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After
receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO,
FIFO, and response proper data/status to USB host.
7. IDE Engine
The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra
DMA mode data transfers.
8. FIFOs
Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong
FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 /
RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE
logic, and re-direct to IDE engine.
9. Control Registers
Control Register configures GL811E to proper operation. For example, CPU can set register to generate
wakeup event, enter suspend, transmits proper USB packet to host.
10. ATA/ATAPI
The GL811E complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information.
11. USB 2.0
The GL811E complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own
design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI)
specification rev. 1.01. Please refer to the specifications for more information.
©2000-2006 Genesys Logic Inc. - All rights reserved.
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