GA20JT12-247_15 Datasheet, PDF (8/12 Pages) GeneSiC Semiconductor, Inc. – OFF Silicon Carbide Junction Transistor

GA20JT12-247
Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady on-
state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage
developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow
through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 7) level to counter
these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. Turn off can be achieved with VGS = 0 V, however a negative gate voltage VGS may be used in order to
speed up the turn-off transition.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA20JT12-247 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and low-
side driving, its datasheet provides additional details about this drive topology.
+12 V
Gate
Signal
+12 V
VCC High
C2 _U3
VGL
C5
GA03IDDJT30-FR4
Gate Driver Board
VCC High RTN
Signal
R1 U1
U2
Signal RTN
VGL
R2
VEE _C6
VGL
R3
VEE
VGH
U5
C9
VEE ^C10
VGL
U6
VEE
D1
C8
CG1
CG2
R4
RG1
RG2
VCC Low
C1 _U4
VCC Low RTN
VGH
C3
C4
VEE
Voltage Isolation Barrier
D
Gate I_{G G}
SiC SJT ^S
Source
Figure 23: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance³ of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA20JT12-247. The steady state current supplied to the gate pin of the GA20JT12-247 with on-board RG = 3.75 Ω, is shown
in Figure 24. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 25.
For the GA20JT12-247, RG must be reduced for ID ≥ ~14 A for safe operation with the GA03IDDJT30-FR4.
For operation at ID ≥ ~14 A, RG may be calculated from the following equation, which contains the DC current gain hFE and the gate-source
saturation voltage VGS,sat (Figure 7).
𝑅𝑅_{𝐺𝐺,𝑚𝑚𝑚𝑚}
=
�4.7𝑉𝑉
−
𝑉𝑉_{𝐺𝐺𝐺𝐺,í µí± í µí± í µí± í µí± í µí± í µí±}  � ∗
𝐼𝐼_{𝐷𝐷} ∗ 1.5
ℎ_{𝐹𝐹𝐹𝐹} (𝑇𝑇,
𝐼𝐼_{𝐷𝐷} )
−
0.6Ω
Jan 2015
Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
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