GA15IDDJT22-FR4 Datasheet, PDF (1/5 Pages) GeneSiC Semiconductor, Inc. – Gate Driver for SiC SJT with Output and Signal Isolation

Isolated Gate Driver
Gate Driver for SiC SJT with Output
and Signal Isolation
Features
 Requires single 12 V voltage supply
 Two-voltage level topology with low drive losses
 High-side drive capable with 2200 V min. supply isolation
 6000 V Signal Isolation (up to 10 s)
 Capable of high Gate Currents with 3 W Maximum Power
Package
 RoHS Compliant
GA15IDDJT22-FR4
V_ISO,min
= 2200 V
P_{Drive, cont}
= 15 W
P_Drive,switch
=
>3W
f_MAX
= TBD
Suitable for driving
 GA50JT12-247
 GA50JT12-247
 GA50SICP12-227
 GA100SICP12-227
Gate Drive Theory of Operation
The SJT transistor is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal
gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 1.
Figure 1: Idealized Gate Current Waveform
Gate Currents, I_G,pk/-I_G,pk and Voltages during Turn-On and Turn-Off
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q_G, for turn-on is supplied by a burst of high
gate current, I_G,on, until the gate-source capacitance, C_GS, and gate-drain capacitance, C_GD, are fully charged.
,
As an example, an I_G,pon ≥ 3 A is required to achieve a 25 ns V_DS fall time for a 800 V switching transition, due to the gate-drain charge, Q_GD of
77 nC for the GA20JT12-247. The I_G,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid
unnecessary drive losses during the steady on-state. In practice, the rise time of the I_G,on pulse is affected by the parasitic inductances, L_par in
the TO-247 package and drive circuit. A voltage developed across the parasitic inductance in the source path, L_s, can de-bias the gate-source
junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the
V_GS,ON level to counter these effects.
A high negative peak current, -I_G,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V_GS = 0 V, a negative gate voltage V_GS may be used in
order to speed up the turn-off transition.
Sep 2014
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