GA100SBJT12-FR4 Datasheet, PDF (1/6 Pages) GeneSiC Semiconductor, Inc. – Double Pulse Test Board

Double Pulse Test Board GA100SBJT12-FR4
Double Pulse Test Board
Features
 1200 V, 100 A Testing
 Low Series Inductance Design
 Wide, 6 oz. Copper Current Traces
 Multiple DUT and FWD Connections for Long Life
 Compatible with GeneSiC Gate Drive Mounting
 Low Resistance and Inductance Gate Drive Connection
VDS, MAX
=
Compatible
ID, MAX
=
 TO-247 Packaged Commercial SJTs
 TO-257 Packaged High Temperature SJTs
 TO-258 Packaged High Temperature SJTs
 TO-46 Packaged High Temperature SJTs
1200 V
100 A
Electrical Characteristics
Parameter
Test Voltage Maximum
Drain Current Maximum
Capacitor Bank
Parasitic Inductance
Maximum Stored Energy
Symbol
V_{DS, MAX}
I_{D, MAX}
C_bank
L_s
E_max
Conditions
HV = 800 V, ID = 6 A
HV = 1200 V
Value
1200
100
5.0
62.5
3.6
Unit Notes
V
A
µF
nH
J
Overview
The GeneSiC Double Pulse Test Board is designed for performing double
pulse switching tests on GeneSiC SiC Junction Transistors (SJT) as well
as other three terminal switching transistors. It is designed using low ESL
capacitors and PCB traces to feature a low parasitic series inductance
(L_S) current path. This is necessary to record data which is most
representative of the device under test (DUT) and minimize testing circuit
distortions. The board is capable of reaching a maximum of
1200 V and 100 A for high power device testing. An external load inductor,
DUT, and free-wheeling diode (FWD) are soldered to the board without
sockets for the lowest possible contact resistance and inductance.
GeneSiC pin compatible gate drive boards may be mounted directly on
to the Test Board for ease of use while also having a short, low inductance
path to the DUT gate pin connection.
Figure 1: GeneSiC Semi Double Pulse Test Board
Figure 2: GeneSiC Semiconductor Switching Test Board Schematic
Sept 2014
http://www.genesicsemi.com/
Pg 1 of 6