NJ8821 Datasheet, PDF (1/5 Pages) Zarlink Semiconductor Inc – FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS

NJ8821
NJ8821
DS3278-1.3
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
The NJ8821 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external control
from a suitable microprocessor..
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8821 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of 230°C to 170°C. The NJ8821MA is available only in
Ceramic DIL package with operating temperature range of
240°C to 185°C.
FEATURES
s Low Power Consumption
s Microprocessor Compatible
s High Performance Sample and Hold Phase Detector
s >10MHz Input Frequency
ORDERING INFORMATION
NJ8821 BA DP Plastic DIL Package
NJ8821 BA MP Miniature Plastic DIL Package
NJ8821 MA DG Ceramic DIL Package
PDA 1
20 CH
PDB 2
19 RB
LD 3
18 MC
F_IN 4
17 DS2
V_SS 5
16 DS1
NJ8821
V_DD 6
15 DS0
OSC IN 7
14 PE
OSC OUT 8
13 NC
D0 9
D1 10
12 D3
11 D2
DP20, MP20
DG20
Fig.1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V_DD2V_SS
Input voltage
20·5V to 7V
Open drain output, pin 3
7V
All other pins
Storage temperature
V_SS20·3V to V_DD10·3V
265°C to 1150°C
(DG package, NJ8821MA)
Storage temperature
255°C to 1125°C
(DP and MP packages, NJ8821)
PROGRAM ¹⁴
ENABLE (PE)
OSC IN ⁷
OSC OUT ⁸
DATA
INPUTS


D0
D1
D2
 D3
9
10
11
12
F_IN ⁴
V_DD ⁶
V_SS ⁵
LATCH SELECT
LOGIC
DATA SELECT INPUTS
DS0 DS1 DS2
15 16 17
TO
INTERNAL
LATCHES
REFERENCE COUNTER
(11BITS)
42
f_r
LATCH 6 LATCH 7 LATCH 8
LATCH 4 LATCH 5
‘A’ COUNTER
(7 BITS)
LATCH 1 LATCH 2 LATCH 3
‘M’ COUNTER
f_v
(10 BITS)
CONTROL LOGIC
Fig.2 Block diagram
RB
CH
19
20
SAMPLE/HOLD
PHASE
DETECTOR
1 _PDA
FREQUENCY/
PHASE
DETECTOR
2 _PDB
3 _{LOCK DETECT (LD)}
V_SS
18
MODULUS
CONTROL
OUTPUT (MC)