MB90370 Datasheet, PDF (96/140 Pages) Fujitsu Component Limited. – 16-bit Proprietary Microcontroller

MB90370/375 Series
19. Parity generator
The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a
parity generator data register (PGDR) , an odd / even parity generation logic and a parity generator control status
register (PGCSR) .
An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the
input data. Either odd or even parity can be generated by setting the PGCSR.
For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “1”, otherwise the parity bit will be set to “0”.
For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “0”, otherwise the parity bit will be set to “1”.
Table shows some examples of odd / even parity generation.
Input data
Parity bit (odd parity)
Parity bit (even parity)
0000 0000B
1
0
0101 0101B
1
0
1000 0000B
0
1
1010 1011B
0
1
(1) Register configuration of parity generator
Parity Generator Data Register
Address : 000018H
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
X
X
X
X
X
X
X
X
Parity Generator Control Status Register
15
14
13
12
11
10
9
8
Address : 000019H
PRTY 




 PSEL
Read/write
Initial value
R






R/W
X






0
Bit number
PGDR
Bit number
PGCSR
96