MB90423G Datasheet, PDF (95/99 Pages) Fujitsu Component Limited. – 16-Bit Original Microcontroller

MB90420G/5G (A) Series
Table 24 String Instructions [10 Instructions]
Mnemonic
MOVS/MOVSI
MOVSD
# ~ RG B
Operation
LH AH I S T N Z V C RMW
2 *²
2 *²
*⁵ *^{3 Byte transfer @AH+ ← @AL+, counter = RW0} – – – – – – – – – –
*⁵ *^{3 Byte transfer @AH– ← @AL–, counter = RW0} – – – – – – – – – –
SCEQ/SCEQI
SCEQD
2 *¹
2 _*¹
*⁵ *^{4 Byte retrieval (@AH+) – AL, counter = RW0}
*⁵ *^{4 Byte retrieval (@AH–) – AL, counter = RW0}
–––––* * * * –
–––––* * * * –
FISL/FILSI
2 _{6m +6 *}⁵ _*^{3 Byte filling @AH+ ← AL, counter = RW0} – – – – – * * – – –
MOVSW/MOVSWI 2 *²
MOVSWD
2 *²
*⁸ *^{6 Word transfer @AH+ ← @AL+, counter = RW0} – – – – – – – – – –
*⁸ *^{6 Word transfer @AH– ← @AL–, counter = RW0} – – – – – – – – – –
SCWEQ/SCWEQI 2 *¹
SCWEQD
2 _*¹
*⁸ *^{7 Word retrieval (@AH+) – AL, counter = RW0} – – – – – * * * * –
*⁸ *^{7 Word retrieval (@AH–) – AL, counter = RW0 – – – – – * * * * –}
FILSW/FILSWI
2 _{6m +6 *}⁸ _*^{6 Word filling @AH+ ← AL, counter = RW0} – – – – – * * – – –
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-
rately for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) × n
*8: 2 × (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
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