MB15E07L Datasheet, PDF (9/23 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler

MB15E07L
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
AAAAAAA
7654321
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Table.5 Prescaler Data Setting
SW
H
L
Prescaler divide ratio
32/33
64/65
Table.6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
(2) Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor
pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is
shown below.
Table.7 FC Bit Data Setting (LDS = “H”)
DO
fr > fp
H
fr < fp
L
FC = High
φR
φP
LD/fout
DO
L
L
L
H
Z*
fout = fr
H
fr = fp
Z*
L
Z*
Z*
* : High impedance
FC = Low
φR
φP
H
Z*
L
L
L
Z*
LD/fout
fout = fp
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