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MB15E05SL Datasheet, PDF (9/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip 2.0 GHz Prescaler
MB15E05SL
Programmable Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CNT A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
CNT : Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note: Data input with MSB first.
[Table 1]
[Table 3]
[Table 4]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio(R)
R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3
0
0
0
0
0
000000011
4
0
0
0
0
0
000000100
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
111111111
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide
ratio(N)
N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
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