MB91305 Datasheet, PDF (79/90 Pages) Fujitsu Component Limited. – 32-bit Microcontroller

MB91305
(13) SDRAM Timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Condi-
tions
Value
Min
Max
Unit Remarks
Output clock cycle time
tCYCSD
⎯
32 MHz
“H” level clock pulse width
tCHSD
MCLK
⎯
12
⎯
ns
“L” level clock pulse width
tCLSD
12
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDCKE
tOHSDCKE
MCLKE
⎯
15
ns
2
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDRAS
tOHSDRAS
SRAS
⎯
15
ns
2
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDCAS
tOHSDCAS
SCAS
⎯
15
ns
2
⎯
ns
MCLK ↑ → output delay time
tODSDWE
⎯
15
ns
SWR
Output hold time
tOHSDWE
2
⎯
ns
⎯
MCLK ↑ → output delay time
tODSDCS
CS6
⎯
15
ns
Output hold time
tOHSDCS
CS7
2
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDA
tOHSDA
A00 to A15
⎯
15
ns
2
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDDQM
tOHSDDQM
DQMUU
DQMUL
⎯
15
ns
2
⎯
ns
MCLK ↑ → output delay time
Output hold time
tODSDD
tOHSDD
D16 to D31
⎯
15
ns
2
⎯
ns
Data input setup time
Data input hold time
tISSDD
15
⎯
ns
D16 to D31 ⎯
tIHSDD
2
⎯
ns
79