MB90660A Datasheet, PDF (77/83 Pages) Fujitsu Component Limited. – 16-bit Proprietary Microcontroller CMOS

MB90660A Series
Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
# ~ RG B
Operation
LH AH I S T N Z V C RMW
1 4 0 (c) word (SP) ← (SP) –2, ((SP)) ← (A) – – – – – – – – – –
1 4 0 (c) word (SP) ← (SP) –2, ((SP)) ← (AH) – – – – – – – – – –
1 4 0 (c) word (SP) ← (SP) –2, ((SP)) ← (PS) – – – – – – – – – –
2 *³ *⁵ *⁴ (SP) ← (SP) –2n, ((SP)) ← (rlst)
––––––––– –
POPW A
POPW AH
POPW PS
POPW rlst
1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) +2 – * – – – – – – – –
1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) +2 – – – – – – – – – –
1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) +2 – – * * * * * * * –
2 *² *⁵ *⁴ (rlst) ← ((SP)), (SP) ← (SP) +2n
––––––––– –
JCTX @A
1 14 0 6× (c) Context switch instruction
––* * * * * * * –
AND CCR, #imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 – – * * * * * * * –
OR CCR, #imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 – – * * * * * * * –
MOV RP, #imm8
MOV ILM, #imm8
2 2 0 0 byte (RP) ←imm8
2 2 0 0 byte (ILM) ←imm8
––––––––– –
––––––––– –
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
23 1
2+ 2+ (a) 1
21 0
2+ 1+ (a) 0
0 word (RWi) ←ear
0 word (RWi) ←eam
0 word(A) ←ear
0 word (A) ←eam
––––––––– –
––––––––– –
–*––––––– –
–*––––––– –
ADDSP #imm8
ADDSP #imm16
2 3 0 0 word (SP) ← (SP) +ext (imm8) – – – – – – – – – –
3 3 0 0 word (SP) ← (SP) +imm16
––––––––– –
MOV A, brgl
MOV brg2, A
2 *¹ 0 0 byte (A) ← (brgl)
2 1 0 0 byte (brg2) ← (A)
Z*–––* *–– –
–––––* *–– –
NOP
1 1 0 0 No operation
––––––––– –
ADB
1 1 0 0 Prefix code for accessing AD space – – – – – – – – – –
DTB
1 1 0 0 Prefix code for accessing DT space – – – – – – – – – –
PCB
1 1 0 0 Prefix code for accessing PC space – – – – – – – – – –
SPB
1 1 0 0 Prefix code for accessing SP space – – – – – – – – – –
NCC
1 1 0 0 Prefix code for no flag change
––––––––– –
CMR
1 1 0 0 Prefix code for common register bank – – – – – – – – – –
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
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