MB90670 Datasheet, PDF (62/106 Pages) Fujitsu Component Limited. – 16-Bit Proprietary Microcontroller

MB90670/675 Series
10. UART0
UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous
communication (start-stop synchronization system). In addition to the normal duplex communication function
(normal mode), UART0 has a master/slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 12 types
External clock input possible
Internal clock (a clock supplied from 16-bit reload timer can be used.)
• Data length: 7 bits to 9 bits selective (with a parity bit)
6 bits to 8 bits selective (without a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request: Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI²OS)
• Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication
possible
(1) Register Configuration
• Status register 0 (USR0)
Address
000021H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
RDRF ORFE PE TDRE RIE TIE
R/W R/W R/W R/W R/W R/W
bit 9
RBF
R/W
bit 8 bit 7. ^{. . . . . . . . . . . .bit} 0
TBF
(UMC0)
R/W
• Mode control register 0 (UMC0)
Address
bit 15. ^{. . . . . . . . . . .} bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
000020H
(USR0)
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
R/W R/W R/W R/W R/W R/W R/W R/W
• Rate and data register 0 (URD0)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7. ^{. . . . . . . . . . . .bit} 0
000023H
BCH RC3 RC2 RC1 RC0 BCH0 P
D8 ^{(UIDR0/UODR0)}
R/W R/W R/W R/W R/W R/W R/W R/W
• Input data register 0 (UIDR0)
Address bit 15. ^{. . .} b.it 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
000022H
(URD0)
D8 D7 D6 D5 D4 D3 D2
bit 1 bit 0
D1 D0
R
• Output data register 0 (UODR)
Address bit 15. ^{. . .} b.it 9 bit 8
000022H
(URD0)
D8
R
R
bit 7 bit 6
D7 D6
R
R
R
R
bit 5 bit 4 bit 3 bit 2
D5 D4 D3 D2
R
R
bit 1 bit 0
D1 D0
W
W
W
W
W
W
W
W
W
R/W : Readable and writable
R : Read only
W: Write only
X : Indeterminate
Initial value
00100000B
Initial value
00000100B
Initial value
00000000B
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
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