MB90394HA Datasheet, PDF (53/72 Pages) Fujitsu Component Limited. – 16-bit Microcontroller

MB90390 Series
(4) UART0/1 and Serial I/O Timing
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Sym-
bol
tSCYC
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → Valid SIN hold time tSHIXI
Serial clock “H” pulse width tSHSL
Serial clock “L” pulse width tSLSH
SCK ↓ → SOT delay time tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → Valid SIN hold time tSHIXE
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Pin
Condition
Value
Min Max
Unit
Re-
marks
SCK0, SCK1, SCK4
8 tCP ⎯ ns
SCK0, SCK1, SCK4,
SOT0, SOT1, SOT4 ^{Internal clock}
−80 +80 ns
operation output
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
pins are
CL = 80 pF + 1 TTL.
100
⎯
ns
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
60 ⎯ ns
SCK0, SCK1, SCK4
4 tCP ⎯ ns
SCK0, SCK1, SCK4
4 tCP ⎯ ns
SCK0, SCK1, SCK4, External clock
SOT0, SOT1, SOT4 operation output
⎯ 150 ns
SCK0, SCK1, SCK4, ^{pins are}
SIN0, SIN1, SIN4 ^{CL = 80 pF + 1 TTL.}
60
⎯
ns
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
60 ⎯ ns
Notes : • Above rating is the case of CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Internal Shift Clock Mode
SCK
SOT
0.8 V
tSLOVI
2.4 V
0.8 V
SIN
tSCYC
2.4 V
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
DS07-13723-8E
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