MB86977 Datasheet, PDF (5/30 Pages) Fujitsu Component Limited. – IP PACKET FORWARDING ENGINE

MB86977
s PIN DESCRIPTION
• Host (SRAM) interface
Pin No.
Pin Name
173 to 184
A2 to A13
15 to 25
29 to 38
42 to 52
DQ0 to DQ31
166
CS_
167
WE_
168
RE_
8
INT_
I/O
I
ADDRESS BUS
Address input
Function
I/O
DATA INPUT/OUTPUT
Data input/output (32 bit)
I
CHIP SELECT
Chip select input
I
WRITE ENABLE
Write operation enable signal (low enable)
I
READ ENABLE
Read operation enable signal (low enable)
O
INTERRUPT
Interrupt indication (low enable)
• RMII interface
Pin No.
Pin Name
164
REF_CLK
150, 151
108, 109
60, 61
102, 103
149
107
59
101
141
127
79
93
137, 138
123, 124
75, 76
89, 90
132
118
70
84
TXD_W [1 : 0]
TXD_D [1 : 0]
TXD_0 [1 : 0]
TXD_1 [1 : 0]
TX_EN_W
TX_EN_D
TX_EN_0
TX_EN_1
RX_ER_W
RX_ER_D
RX_ER_0
RX_ER_1
RXD_W [1 : 0]
RXD_D [1 : 0]
RXD_0 [1 : 0]
RXD_1 [1 : 0]
CRS_DV_W
CRS_DV_D
CRS_DV_0
CRS_DV_1
I/O
Function
REFERENCE CLOCK
I Reference clock from the PHY device.
The frequency is 50 MHz for both 10 Mbps and 100 Mbps.
TRANSMIT DATA
O The two bit data is transmitted to PHY devices through this
interface. Synchronous with REF_CLK.
TRANSMIT ENABLE
O Active high signal indicates that TX data is valid.Synchronous with
REF_CLK.
RECEIVE ERROR
I
Active high signal indicates that an invalid symbol has been
detected within a received packet.This input is ignored when the
CRS_DV signal is inactive.
RECEIVE DATA
I The two bit data is received from the PHY device through this
interface.
CARRIER SENSE / RECEIVE DATA VALID
I
PHY Device inputs active high signal when the interface is
receiving data. Asynchronous assertion/deassertion by PHY
device upon carrier detection/carrier invalid.
Note : The logical AND of the TX_EN and CRS_DV signals indicate a collision during half duplex modes.
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