MB1502 Datasheet, PDF (5/15 Pages) Fujitsu Component Limited. – SERIAL INPUT PLL FREQUENCY SYNTHESIZER

Control bit
LSB
MSB
CSSSSSSSSSSSSSSSSSS
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Divide ratio of swallow
counter setting bit
Divide ratio of programmable
counter setting bit
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
A
0
1
•
127
SSSSSSS
7654321
0000000
0000001
•••••••
1111111
NOTE: Divide ratio: 0 to 127
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio
N
16
17
•
2047
SSSSSSSSSSS
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
00000010001
00000010001
•••••••••••
11111111111
NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
PULSE SWALLOW FUNCTION
f_vco =
f_VCO:
N:
A:
f_OSC:
R:
P:
[(PxN)+A] x f_osc ÷ R
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
Preset divide ratio of binary 7-bit swallow counter (0≤A≤127, A<N)
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
Preset modulus of external dual modulus prescaler (64 or 128)
MB1502
5