FT232BM Datasheet, PDF (5/24 Pages) Future Technology Devices International Ltd. – USB UART ( USB - Serial) I.C.

3.0 Block Diagram ( simplified )
FT232BM USB UART ( USB - Serial) I.C.
VCC
3V3OUT
PWRCTL
3.3 Volt
LDO
Regulator
SLEEP#
PWREN#
Dual Port TX
Buffer
128 bytes
48MHz
USBDP
USBDM
USB
Transceiver
Serial Interface
Engine
( SIE )
USB
Protocol Engine
UART
FIFO Controller
Baud Rate
Generator
UART
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
USB DPLL
XTOUT
XTIN
6MHZ
Oscillator
x8 Clock
Multiplier
Dual Port RX
Buffer
384 Bytes
48MHz
12MHz ^RESET#
3V3OUT
RESET
GENERATOR
EEPROM
Interface
TXLED#
RXLED#
EECS
EESK
EEDATA
RSTOUT#
TEST
GND
3.1 Functional Block Descriptions
• 3.3V LDO Regulator
The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output
buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also
provides 3.3v power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and
the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3v nominal
at a current of not greater than 5mA could also draw it’s power from the 3V3OUT pin if required.
• USB Transceiver
The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The
output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection.
• USB DPLL
The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data
signals to the SIE block.
• 6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz reference clock input to the X8 Clock multiplier from an external
6MHz crystal or ceramic resonator.
DS232B Version 1.1 © Future Technology Devices Intl. Ltd. 2002
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