CS401 Datasheet, PDF (5/8 Pages) Fujitsu Component Limited. – Standard Cell CS401 Series

CS401 Series
■ DESIGN METHODS
Fujitsu Semiconductor's Reference Design Flow provides the following functions that help reduce the
development time of large scale, high quality LSIs.
• Statistical Static Timing Analysis (SSTA) improves timing convergence.
• Physical Prototyping enables more accurate estimation of highly reliable designs.
• Layout synthesis with optimized timing is realized by Physical Synthesis Tool.
• High accuracy design environment where drop in power supply voltage, signal noise, delay penalty and
crosstalk are considered
• I/O design environment (power line design, assignment and selection of I/Os, package selection) where
noise is considered
■ PACKAGES
The CS401 series can use the same packages that were available for the previous series, allowing a smooth
transition from previously developed models. For details of delivery times, contact the sales representative.
• FBGA packages
• PBGA packages
• TEBGA packages
• FC-BGA packages
DS601-00001-2v0-E
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