MB95120MB Datasheet, PDF (44/80 Pages) Fujitsu Component Limited. – 8-bit Microcontrollers

MB95120MB Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Condi-
tion
Value
Min
Max
Unit
Remarks
Source clock cycle time*¹
(Clock before setting
tSCLK
division)
When using main clock
61.5
2000
ns
Min : FCH = 8.125 MHz,
PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
When using sub clock
7.6
61.0
µs
Min : FCL = 32 kHz,
PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
Source clock frequency
FSP
0.50 16.25 MHz When using main clock
FSPL
⎯ _{16.384 131.072 kHz When using sub clock}
Machine clock cycle time*²
(Minimum instruction
execution time)
tMCLK
61.5
7.6
32000
976.5
When using main clock
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
When using sub clock
µs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
Machine clock frequency
FMPL
0.031 16.250 MHz When using main clock
1.024 131.072 kHz When using sub clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
44
SCLK
(source clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
(machine clock)