MB89850R Datasheet, PDF (41/48 Pages) Fujitsu Component Limited. – 488-bit Proprietary Microcontroller

MB89850R Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
~#
Operation
TL TH AH N Z V C OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
3 2 (dir) ← (A)
– – – ––––
45
4 2 ( (IX) +off ) ← (A)
– – – ––––
46
4 3 (ext) ← (A)
– – – ––––
61
3 1 ( (EP) ) ← (A)
– – – ––––
47
3 1 (Ri) ← (A)
– – – – – – – 48 to 4F
2 2 (A) ← d8
AL – – + + – –
04
3 2 (A) ← (dir)
AL – – + + – –
05
4 2 (A) ← ( (IX) +off)
AL – – + + – –
06
4 3 (A) ← (ext)
AL – – + + – –
60
3 1 (A) ← ( (A) )
AL – – + + – –
92
3 1 (A) ← ( (EP) )
AL – – + + – –
07
3 1 (A) ← (Ri)
AL – – + + – – 08 to 0F
4 3 (dir) ← d8
– – – ––––
85
5 3 ( (IX) +off ) ← d8
– – – ––––
86
4 2 ( (EP) ) ← d8
– – – ––––
87
4 2 (Ri) ← d8
– – – – – – – 88 to 8F
4 2 (dir) ← (AH),(dir + 1) ← (AL)
– – – ––––
D5
5 2 ( (IX) +off) ← (AH),
– – – ––––
D6
( (IX) +off + 1) ← (AL)
5 3 (ext) ← (AH), (ext + 1) ← (AL)
– – – ––––
D4
4 1 ( (EP) ) ← (AH),( (EP) + 1) ← (AL) – – – – – – –
D7
2 1 (EP) ← (A)
– – – ––––
E3
3 3 (A) ← d16
AL AH dH + + – –
E4
4 2 (AH) ← (dir), (AL) ← (dir + 1)
AL AH dH + + – –
C5
5 2 (AH) ← ( (IX) +off),
AL AH dH + + – –
C6
(AL) ← ( (IX) +off + 1)
5 3 (AH) ← (ext), (AL) ← (ext + 1)
AL AH dH + + – –
C4
4 1 (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) AL AH dH + + – –
93
4 1 (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL AH dH + + – –
C7
2 1 (A) ← (EP)
– – dH – – – –
F3
3 3 (EP) ← d16
– – – ––––
E7
2 1 (IX) ← (A)
– – – ––––
E2
2 1 (A) ← (IX)
– – dH – – – –
F2
2 1 (SP) ← (A)
– – – ––––
E1
2 1 (A) ← (SP)
– – dH – – – –
F1
3 1 ( (A) ) ← (T)
– – – ––––
82
4 1 ( (A) ) ← (TH),( (A) + 1) ← (TL)
– – – ––––
83
3 3 (IX) ← d16
– – – ––––
E6
2 1 (A) ← (PS)
– – dH – – – –
70
2 1 (PS) ← (A)
– – – ++++
71
3 3 (SP) ← d16
– – – ––––
E5
2 1 (AH) ↔ (AL)
– – AL – – – –
10
4 2 (dir): b ← 1
– – – – – – – A8 to AF
4 2 (dir): b ← 0
– – – – – – – A0 to A7
2 1 (AL) ↔ (TL)
AL – – – – – –
42
3 1 (A) ↔ (T)
AL AH dH – – – –
43
3 1 (A) ↔ (EP)
– – dH – – – –
F7
3 1 (A) ↔ (IX)
– – dH – – – –
F6
3 1 (A) ↔ (SP)
– – dH – – – –
F5
2 1 (A) ← (PC)
– – dH – – – –
F0
Note During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F²MC-8 family)
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