MB15F72UV Datasheet, PDF (4/26 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F72UV
s PIN DESCRIPTION
Pin no.
Pin name I/O
BCC
Descriptions
1
GND  Ground for OSC input buffer and the shift register circuit.
2
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
3
XfinIF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
4
GNDIF  Ground for the IF-PLL section.
5
VCCIF

Power supply voltage input pin for the IF-PLL section, the OSC input buffer and the
shift register circuit.
6
DOIF O Charge pump output pin for the IF-PLL section.
Power saving mode control for the IF-PLL section. This pin must be set at “L” when
7
PSIF
I the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
Lock detect signal output (LD) /phase comparator monitoring
8
LD/fout O output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
Power saving mode control pin for the RF-PLL section. This pin must be set at “L”
9
PSRF I when the power supply is started up. (Open is prohibited.)
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
10
DORF O Charge pump output pin for the RF-PLL section.
11
VCCRF  Power supply voltage input pin for the RF-PLL section
12
GNDRF  Ground for the RF-PLL section
13
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
14
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
15
LE
I When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in the serial data.
Serial data input pin (with the schmitt trigger circuit)
16
Data I Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in the serial data.
17
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
18
OSCIN
I
The programmable reference divider input. TCXO should be connected with an AC
coupling capacitor.
4