MB90560_08 Datasheet, PDF (34/92 Pages) Fujitsu Component Limited. – 16-bit Proprietary Microcontrollers

MB90560/565 Series
3. Watchdog Timer
• The watchdog timer is a timer/counter used to detect faults such as program runaway.
• The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or watch timer.
• Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,
the CPU is reset.
• Interval time for the watchdog timer
HCLK : Oscillation Clock (4 MHz)
Min.
Max.
Approx. 3.58 ms
Approx. 4.61 ms
Approx. 14.33 ms
Approx. 18.30 ms
Approx. 57.23 ms
Approx. 73.73 ms
Approx. 458.75 ms
Approx. 589.82 ms
Clock Period
2¹⁴ ± 2¹¹ / HCLK
2¹⁶ ± 2¹³ / HCLK
2¹⁸ ± 2¹⁵ / HCLK
2¹⁸ ± 2¹⁵ / HCLK
Notes : • The difference between the maximum and minimum watchdog timer interval times is due to the timing when
the counter is cleared.
• As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or watch
timer, clearing the timebase timer (when operating on HCLK) or the watch timer (when operating on SCLK)
lengthens the time until the watchdog timer reset is generated.
• Watchdog timer count clock
WTC : WDCS
“0”
“1”
HCLK : Oscillation clock
PCLK : PLL clock
Prohibited setting
Count the timebase timer output.
• Events that stop the watchdog timer
1 : Stop due to a power-on reset
2 : Watchdog reset
• Events that clear the watchdog timer
1 : External reset input from the RST pin.
2 : Writing “0” to the software reset bit.
3 : Writing “0” to the watchdog control bit (second and subsequent times) .
4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .
5 : Changing to timebase timer mode (clears the watchdog timer and temporarily halts the count) .
6 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .
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DS07-13715-5E