MB85RS1MTPW-G Datasheet, PDF (3/40 Pages) Fujitsu Component Limited. – 1M (128 K × 8) Bit SPI

MB85RS1MT
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
1
1E
This is an input pin to make chips select. When CS is “H” level, device is in deselect
CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code. The Chip Select pin is pulled up internally to the VDD pin.
Write Protect pin
3
2B
WP
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN. See “■ WRITING
PROTECT” for detail.
Hold pin
7
2D
HOLD
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
do not care. While the hold operation, CS has to be retained “L” level.
6
3C
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
3A
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
2
1C
Serial Data Output pin
SO This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
3E
VDD Supply Voltage pin
4
1A
VSS Ground pin
DS501-00022-6v0-E
3