MB15F74UL Datasheet, PDF (3/26 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F74UL
s PIN DESCRIPTION
Pin no.
Pin
name
I/O
Descriptions
1
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
2
XfinIF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
3
GNDIF  Ground pin for the IF-PLL section.
4
VCCIF

Power supply voltage input pin for the IF-PLL section (except for the charge pump
circuit) , the shift register and the oscillator input buffer.
Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when
5
PSIF I the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode/PSIF = “L” ; Power saving mode
6
VpIF  Power supply voltage input pin for the IF-PLL charge pump.
7
DoIF O Charge pump output for the IF-PLL section.
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The
8 LD/fout O output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal
9
DoRF O Charge pump output for the RF-PLL section.
10
VpRF  Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be set at “L” when the
11
PSRF I power supply is started up. (Open is prohibited. )
PSRF = “H” ; Normal mode/PSRF = “L” ; Power saving mode
12
VCCRF

Power supply voltage input pin for the RF-PLL section (except for the charge pump
circuit)
13 GNDRF  Ground pin for the RF-PLL section
14
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
15
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
16
LE
I When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
Serial data input pin (with the schmitt trigger circuit)
17
Data I Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
19
OSCIN
I
The programmable reference divider input pin. TCXO should be connected with an AC
coupling capacitor.
20
GND  Ground pin for OSC input buffer and the shift register circuit.
3