MB3773 Datasheet, PDF (24/29 Pages) Fujitsu Component Limited. – Power Supply Monitor with Watch-Dog Timer

MB3773
EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency
VCC (5 V)
R2
1
8
RESET
2
7
CT
3
6
4
5
R1=10 kΩ
RESET
CK
Tr1
C2
GND
Notes : • This is an example application to limit upper frequency fH of clock pulses sent from
the microprocessor.
If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.
(The lower frequency has already been set using CT.)
• When a clock pulse such as shown below is sent to terminal CK, a short T2 prevents C2 voltage
from reaching the CK input threshold level ( =: 1.25 V), and will cause a reset signal to be output.
The T1 value can be found using the following formula :
T1 =: 0.3 C2R2
where VCC = 5 V, T3 ≥ 3.0 µs, T2 ≥ 20 µs
T2
CK waveform
T3
C2 voltage
T1
Example : Setting C and R allow the upper T1 value to be set (Refer to the table below).
C
0.01 µF
0.1 µF
R
10 kΩ
10 kΩ
T1
30 µs
300 µs
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