CS201 Datasheet, PDF (2/9 Pages) Vishay Siliconix – Capacitor Networks, Single-In-Line, Conformal Coated SIP D Profile

CS201 Series
(Continued)
• Improve timing convergence by using Statistical Static Timing Analysis (SSTA)
• Design For Manufacturing (DFM) enables stable product-supply and reduced variation
• Optimum package range : FBGA, PBGA, TEBGA, FC-BGA
*1: To realize this memory, the “1T-SRAM-Q ^®” technology by MoSys Inc. was used
*2: “CoolAdjust ^TM” is low power solution presented by Fujitsu.
Note : Some of the features are not available yet.
■ MACRO LIBRARIES (including macros currently being prepared)
1. Logic cells (about 400 types)
Library sets having three different threshold voltages of core transistors.
• Adder
• AND
• AND-OR
• AND-OR Inverter
• Buffer
• Clock Buffer
• Decoder
• Delay Buffer
• ENOR
• EOR
• Inverter
• Latch
• NAND
• NOR
• OR
• OR-AND
• OR-AND Inverter
• SCAN Flip flop
• Non-SCAN Flip Flop • Multiplexer
• Others
2. IP macros
The following macros will be made available for the CS201 series.
CPU/DSP
ARM™* cores(ARM7/ARM9/ARM11),Peripherals IP
Mixed signal macro
ADC, DAC, OPAMP, others
Compiled macro
SRAM (1 Port, 2 Port), 1 ROM, product sum calculators
Large capacity memory
1T-SRAM-Q ^®
PLL
Analog PLL
* : ARM is the trademark of ARM Limited.
3. Special I/O interface macro
Interface macro (PHY)
LVDS, SSTL2, SSTL18, PCI, I²C, others
Interface macro (controller)
USB2.0 Device/host, Serial ATA, PCI-Express, DDR2, HDMI,
others
2