MB91265 Datasheet, PDF (16/54 Pages) Fujitsu Component Limited. – 32-bit Proprietary Microcontroller

MB91265 Series
Caution for operation during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this device, the device
may continue to operate at the free-run frequency of the PLL’s internal self-oscillating oscillator circuit.
Performance of this operation, however, cannot be guaranteed.
External clock
When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously.
If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So,
when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the collision
of output.
The following figure shows using an external clock.
X0
X1
MB91265 series
Using an external clock
C pin
A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator.
C
MB91265 series
VSS
GND
0.1 µF
ACC pin
A capacitor of approximately 0.1 µF should be inserted between the ACC pin and the AVSS pin as this product
has built-in A/D converter.
ACC
MB91265 series
AVSS
0.1 µF
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