MB91360G_05 Datasheet, PDF (141/239 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller

MB91360G Series
13. External Interrupt/NMI Control Block
The external interrupt/NMI controller controls external interrupt requests input from the NMIX and INT0 to INT7
pins.
Detection of “H” levels, “L” levels, rising edges, or falling edges can be selected (except for the NMI) .
The external interrupt/NMI controller can also be used for DMA requests.
This section lists the registers of the controller and provides its block diagram.
(1) Register configuration of the external interrupt NMI controller
External interruption permission register (ENIR)
Bit 7
6
5
4
3
2
1
0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
External interruption factors register (EIRR)
Bit 15
14
13
12
11
10
9
8
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Request level setting register (ELVR)
Bit 15
14
13
12
11
10
9
8
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Bit 7
6
5
4
3
2
1
0
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
(2) Block diagram
R-bus
8
Enable interrupt request register
Interrupt request
9
Gate
Request F/F
Edge detect
9
circuit
8
External interrupt request register
8
External level register
INT0 to 7
NMIX
141