MB3793-42PNF-G Datasheet, PDF (13/23 Pages) Fujitsu Component Limited. – POWER-VOLTAGE MONITORING IC WITH WATCHDOG TIMER

MB3793-42
s OPERATION SEQUENCE
The operation sequence is explained by using “s TIMING DIAGRAM 1. Basic operation (Positive clock pulse)”.
The following item numbers correspond to the numbers in “s TIMING DIAGRAM 1. Basic operation (Positive
clock pulse)”.
(1) When the power voltage (VCC) reaches about 0.8 V (VCCL), a reset signal is output.
(2) When VCC exceeds the rising-edge detection voltage (VSH), charging of power-on reset hold time setting
capacitance (CTP) is started. VSH is about 4.3 V.
(3) When the voltage at the CTP terminal setting the power-on reset hold time exceeds the threshold voltage
(Vth), resetting is canceled and the voltage at the RESET terminal changes to High level to start charging of
the watchdog timer monitoring time setting capacitance (CTW). Vth is about 3.6 V.
The power-on reset hold time (tPR) can be calculated by the following equation.
tPR (ms) ≈ A × CTP (µF)
Where, A is about 1300.
(4) When the voltage at the CTW terminal setting the monitoring time reaches High level (VH), CTW switches to
discharging from charging. VH is about 1.24 V (reference value).
(5) When clock pulses are input to the CK2 terminal during CTW discharging after clock pulses are input to the
CK1 terminal—positive-edge trigger, CTW switches to charging.
(6) If clock pulse input does not occur at either the CK1 or CK2 clock terminals during the watchdog timer
monitoring time (tWD), the CTW voltage falls below Low level (VL), a reset signal is output, and the voltage at
the RESET terminal changes to Low level. VL is about 0.24 V.
tWD can be calculated from the following equation.
tWD (ms) ≈ B × CTW (µF) + C × CTP (µF)
Where, B is about 1500. C is about 3; it is much smaller than B.
Hence, when CTP / CTW ≤ 10, the calculation can be simplified as follows:
tWD (ms) ≈ B × CTW (µF)
(7) When the voltage of the CTP terminal exceeds Vth again as a result of recharging CTP, resetting is canceled
and the watchdog timer restarts monitoring.
The watchdog timer reset time (tWR) can be calculated by the following equation.
tWR (ms) ≈ D × CTP (µF)
Where, D is about 100.
(8) When VCC falls below the rising-edge detection voltage (VSL), the voltage of the CTP terminal falls and a reset
signal is output, and the voltage at the RESET terminal changes to Low level. VSL is about 4.2 V.
(9) When VCC exceeds VSH, CTP begins charging.
(10)When the voltage of the CTP terminal exceeds Vth, resetting is canceled and the watchdog timer restarts.
(11)When an inhibition signal is input (INH terminal is High level), the watchdog timer is halted forcibly.
In this case, VCC monitoring is continued without the watchdog timer.
The watchdog timer does not function unless this inhibition input is canceled.
(12)When the inhibition input is canceled (INH terminal is Low level), the watchdog timer restarts.
(13)When the VCC voltage falls below VSL after power-off, a reset signal is output.
(14)When the power voltage (VCC) falls below about 0.8 V (VCCL) , a reset signal is released.
Similar operation is also performed for negative clock-pulse input (“s TIMING DIAGRAM 2. Basic operation
(Negative clock pulse)”).
Short-circuit the clock terminals CK1 and CK2 to monitor a single clock. The basic operation is the same but
the clock pulses are monitored at every other pulse (s TIMING Diagram 3. Single-clock input monitoring).
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