MB88141A Datasheet, PDF (12/22 Pages) Fujitsu Component Limited. – D/A Converter for Digital Tuning (Compatible with I2C Bus)

MB88141A
s TIMING DIAGRAM (I²C BUS SPECIFICATIONS)
"Start"
Data
"Acknowledge"
condition
change
response
SDA
input
S6 S5 S4 S3 S2 S1 S0 R/W ACK C7 C6 C5
SCL
input
12345
6 7 8 9 10 11 12
AO1
to
AO12
D0 to D7
output
D0 to D7
input
SDA
output
Analog output
HiZ state
HiZ input
HiZ state
Load data
DX
"Acknowledge"
response
ACK D7 D6 D5
"Acknowledge"
response
C0 ACK D7 D6
17 18 19 20
Load data
"Acknowledge" "Stop"
response
condition
D0 ACK
26 27
Delay
Delay
Digital output
D0
D7 D6
D0
D7
Note:
• The SDA input acknowledge response (ACK) is an output signal from the MB88141A.
• The D0-D7 input and output timing represent the timing of switching to write and read operations respectively.
Also, D0-D7 input remains in HiZ state between the end of a read operation and the acknowledgment of the
next I/O write signal.
s ANALOG OUTPUT VOLTAGE RANGE
R-2R ladder circuit
VDD1&VDD2
Operating Amp circuit
VCC ( = VDD1, VDD2)
VSS1&VSS2
Analog output range
GND ( = VSS1, VSS2)
12