MB40C328V Datasheet, PDF (12/16 Pages) Fujitsu Component Limited. – 8-bit 100 MSPS A/D Converter

MB40C328V
s TIMING DIAGRAM 4
Two-phase CLK input mode (CLKA, CLKB)
• CLK = “L” (DVSS) or “H” (DVDDI)
• CLKA = CLKB = 50 MHz (max)
• CKSEL = “L” (AVSS)
• DSEL = “L” (DVSS)
• RESET = “H” (DVDDI) or “L” (DVSS)
• CE = “L” (AVSS)
• OE = “L” (DVSS)
VIHD
CLKA input
VILD
VIHD
CLKB input
VILD
DA0 to DA7
tWD^−
tWD⁺
N(Ach)
tWD⁺
tr
tf
DVDD − 0.5 V
0.5 V
1.5 V
tWD^−
tr
tf
DVDD − 0.5 V
0.5 V
1.5 V
N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)
VINA input
tAD
tAD
VOHD
DA0 to DA7
VOLD
VOHD
DB0 to DB7
VOLD
N−6
N−7
VOHD
CLKOA
VOLD
N−4
N−5
tpdD(max)
tpdD(typ)
tpdD(min)
N−2
N
DVDD−0.4 V
0.4 V
tpdD(max)
tpdD(typ)
tpdD(min)
N−3
N−1
tpdDO(max)
tpdDO(typ)
tpdDO(min)
N+2
N+1
DVDD − 0.4 V
0.4 V
DVDD − 0.4 V
0.4 V
VOHD
CLKOB
VOLD
ALL “L” fix
• VINA input — Sampling (A ch) at CLKA falling
Sampling (B ch) at CLKB falling
• DA0 to DA7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising
• DB0 to DB7 — Output (after 3 CLK + tpdD from Sampling) at CLKB rising
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